Traditional semiconductor dram cell failure has been found to be predominantly due to leakage to the substrate and leakage to the wordline due to poor gate oxide integrity which in turn is due to process defects. The problem is present in systems up to the megabit level. Many test algorithms are available today which identify those devices which are marginal to such defects. With the shrinking of the transistor channel length (sub micron) from 4 mb and beyond, leakage from cell to bitline is becoming a significant factor.
Prior arrangements have been devised to test for such a failure mechanism. However, the test time taken is much too long, making it difficult to implement in a production type test program.
Accordingly, a need exists in the art for a test system and method which tests for leakage between cell and bitline and which does so in a minimum amount of time.
A further need exists in the art for such a system which insures that all cell/bitlines have been exercised and tested.